In this paper a new phase-frequency detector is proposed using transmission gates which can detect phase difference less than 500ps. In other word, the proposed Phase-frequency Detector (PFD) can work in frequencies higher than 1. 7 GHz, whereas a conventional PFD operates at frequencies less than 1. 1 GHz. This new architecture is designed in TSMC 0. 13um CMOS Technology. Also, the proposed PFD achieves a capture range approximately twice that of conventional PFDs. The simulation results support the theoretical predictions. To validate correct performance of this novel PFD, it is then used in a conventional delay locked loop structure.

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occupies very little area. Phase-locked loops (PLLs) and delay-locked loops (DLLs) are blocks that are commonly used in telecommunication applications. One of the most important parts in DLL and PLL is the phase-frequency detector. Therefore, the design of this circuit in QCA technology is of great importance. In this paper, two new phase-frequency detectors sensitive to falling and rising edge have been introduced in QCA technology. Both of the designs are composed of 104 cells; occupy only 0. 13 μ m2 of an area and 1. 5 QCA clock cycles latency. The designs are in one layer and all the inputs and outputs are available to be used by another circuit.

Achieving low power consumption and low delay are the most important goals that efforts have been made to reach. In this paper, the process of designing and optimizing the Phase Frequency Detector (PFD) performance at the integrated circuits (IC) level has been proposed using carbon nanotubes. In the proposed method, by using carbon nanotube transistors, improvements have been made in the output parameters of the phase detector. Failure to use flip-flops and the simple circuit structure will significantly increase speed and reduce power consumption. Post-layout simulation for 180nm CMOS technology and simulation results for 32nm Carbon Nanotube Field-Effect Transistor (CNTFET) technology is presented. The proposed CMOS 28T phase detector circuit, by injecting 30mV peak-to-peak power supply noise has 5× better operating frequency of the conventional circuit, and it has a 10% improvement in power consumption of the conventional one. Also, with carbon nanotubes, the frequency has increased 4 times, and the power consumption has improved significantly. In this case, the power consumption is 1.76 microwatts, and the operating frequency is 20 GHz. Open-loop design and elimination of the reset path, and attention to delays to remove the dead zone are the proposed circuit's top features compared with the traditional design methods.

We have developed the effective algorithm for detecting digital binary phase-shift keyed signals. This algorithm requires a small number of arithmetic operations over the signal period. It can be relat ively easy implemented based on the modern programmable logic devices. It also provides high interference immunity by identifying signal presence when signal-to-noise ratio is much less that its working value in the receiving path. The introduced detector has int rinsic frequency selectivity and allows us to form the est imate of the noise level to realize the adaptive determination of decision threshold. In order to get confirmation of the detector operability and performance, we suggest the expressions for false alarm and missing probabilities. In addit ion, we have examine, both theoretically and experimentally, the influence of the detector parameters on its characterist ics.

In this paper, three different regimes including annular, stratified and homogeneous in the range of 5%-90% void fraction, were simulated by Mont Carlo N-Particle (MCNP) Codes. In simulated structure, a cesium 137 source and two Nal detectors were used to record received photons. In this study, the Fast Fourier Transform (FFT) was applied to the registered signals from two detectors in order to analyze in the frequency domain. Several features of signals in the frequency domain were extracted using average value of fast Fourier transform, the amplitude of dominant frequency, kurtosis, Standard Deviation (STD), RMS (Root Mean Square) and Variance. The same features were extracted from analyzed signals of both detectors in order to find the best separation patterns. These extracted features were used as inputs of artificial neural networks (ANNs) to increase the efficiency of two-phase flowmeters. Two multi-layer perceptrons (MLP) neural networks were implemented in MATLAB software in order to classify flow regimes (annular, stratified and homogeneous) and predict the void fraction. All of the training and testing data were obtained correctly and the mean relative error percentage of the predicted void fraction was 1/15 %.

There is a growing interest in the optimal design of the phase locked loops, because these circuits are widely used in communication and electronic circuits. Undoubtedly the most important objectives in designing PLLs (phase locked loops) are low power consumption and low delay. In this paper, the process of designing and the optimization of PFD (one of the main part in PLLs) are proposed by using particle swarm optimization (PSO) algorithm. In the proposed method, instead of carrying out the frequent experiments and simulations based on trial and error to achieve the desired parameters of the phase frequency detector, effective variables are sent to the PSO algorithm and optimization process is done by this algorithm. The results show a remarkable ability of this heuristic method to find transistors sizing for optimal power consumption and delay.

Nowadays, in the modern wars, radars have faced with many threats. Therefore, low probability of interception (LPI) capability is considered as an important factor in military radars. On the other hand, research on the interception of their signals is started and so far several methods are presented for detection of these signals. By using of time-frequency techniques, we can estimate signal parameters such as carrier frequency, Modulation bandwidth, and its period, in addition of detection of LPI signal. In this paper, the proposed detector architecture uses time-frequency techniques including Wigner-Ville and Choi- Williams distributions for detection of some LPI radar waveforms with Phase Shift Keying (PSK) modulation such as Barker code, Frank code and P1-P4 codes to compare an interception receiver and matched-filter detector in LPI radar receiver with assumption of Additive White Gaussian Noise (AWGN). Then, Power Function graphs for proposed intercept receiver and LPI radar receiver are depicted and compared, which indicate that we obtain desirable results by using of this technique in the intercept receiver.

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.

Quantum-dot cellular automata (QCA) technology is an alternative to overcoming the constraints of CMOS technology. In this paper, a new structure for D-type latch is presented in QCA technology with set and reset terminals. The proposed structure, despite having the set and reset terminals, has only 35 quantum cells, a delay equal to half a cycle of clocks and an occupied area of 39204 nm2. Then, this structure has been used to implement D-type flip-flops that are sensitive to the rising, falling, and both edges. For example, the proposed structure of the rising edge D-type flip-flop has a 55 quantum cells with a delay of 0. 75 clock cycles and an occupied area of 61404 nm2. In order to prove the proposed circuit behavior in more complex circuits, these structures have been used in the form of phase-frequency detectors, frequency dividers, and counters. Simulation of power parameters has been done for proposed structures.